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» A Novel Metric for Interconnect Architecture Performance
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ASPDAC
2006
ACM
118views Hardware» more  ASPDAC 2006»
13 years 11 months ago
A probabilistic analysis of pipelined global interconnect under process variations
— The main thesis of this paper is to perform a reliability based performance analysis for a shared latch inserted global interconnect under uncertainty. We first put forward a ...
Navneeth Kankani, Vineet Agarwal, Janet Meiling Wa...
SLIP
2004
ACM
13 years 11 months ago
Optical solutions for system-level interconnect
Throughput, power consumption, signal integrity, pin count and routing complexity are all increasingly important interconnect issues that the system designer must deal with. Recen...
Ian O'Connor
IEEEHPCS
2010
13 years 4 months ago
Analytical modeling and evaluation of network-on-chip architectures
Network-on-chip (NoC) architectures adopted for Systemon-Chip (SoC) are characterized by different trade-offs between latency, throughput, communication load, energy consumption, ...
Suboh A. Suboh, Mohamed Bakhouya, Jaafar Gaber, Ta...
IFIP
2003
Springer
13 years 11 months ago
A Novel Energy Efficient Communication Architecture for Bluetooth Ad Hoc Networks
Bluetooth is a promising wireless technology aiming at supporting electronic devices to be instantly interconnected into short-range ad hoc networks. The Bluetooth medium access co...
Carlos de M. Cordeiro, Sachin Abhyankar, Dharma P....
ICCSA
2005
Springer
13 years 11 months ago
A Novel Hierarchical Routing Protocol for Wireless Sensor Networks
Abstract. In this paper, we propose a novel hierarchical routing protocol for a large wireless sensor network (WSN) wherein sensors are arranged into a multi-layer architecture wit...
Trong Thua Huynh, Choong Seon Hong