ASPDAC 2006 - PDF Preprint Papers

ASPDAC 2006 Asia and South Pacific Design Automation Conference

Teaser Browsing | Click Here

Title Browsing | Click Here

Wall of Fame | Most Viewed ASPDAC-2006 Paper

click to vote

ASPDAC
2006
ACM

726views Hardware» more ASPDAC 2006»

Newton: a library-based analytical synthesis tool for RF-MEMS resonators

13 years 8 months ago

Download www.eecs.umich.edu

Newton is a library-based CAD tool with an analytical synthesis engine which has been developed to support the direct synthesis of the physical design and an electromechanically eq...

Michael S. McCorquodale, James L. McCann, Richard ...

claim paper

Read More »

Disclaimer and Copyright Notice

Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.

Id	Views	Title	Status

1	726	Newton: a library-based analytical synthesis tool for RF-MEMS resonators	claim
2	288	Algorithms and DSP implementation of H.264/AVC	claim
3	230	Statistical Bellman-Ford algorithm with an application to retiming	claim
4	178	Hardware architecture design of an H.264/AVC video codec	claim
5	176	Conversion of reference C code to dataflow model: H.264 encoder case study	claim
6	176	Closed form solution for optimal buffer sizing using the Weierstrass elliptic function	claim
7	173	Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking	claim
8	169	A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication	claim
9	166	Temperature-aware routing in 3D ICs	claim
10	159	Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology	claim
11	159	An anytime symmetry detection algorithm for ROBDDs	claim
12	158	Analysis of scratch-pad and data-cache performance using statistical methods	claim
13	158	Process-induced skew reduction in nominal zero-skew clock trees	claim
14	157	Delay modeling and static timing analysis for MTCMOS circuits	claim
15	155	Delay defect screening for a 2.16GHz SPARC64 microprocessor	claim
16	153	Diagonal routing in high performance microprocessor design	claim
17	148	An automated design flow for 3D microarchitecture evaluation	claim
18	148	TAPHS: thermal-aware unified physical-level and high-level synthesis	claim
19	146	A fixed-die floorplanning algorithm using an analytical approach	claim
20	145	FSM-based transaction-level functional coverage for interface compliance verification	claim
21	144	Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits	claim
22	143	Constraint-driven bus matrix synthesis for MPSoC	claim
23	143	CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model	claim
24	141	Depth-driven verification of simultaneous interfaces	claim
25	140	A cycle accurate power estimation tool	claim
26	140	Analysis and optimization of gate leakage current of power gating circuits	claim
27	140	A 52mW 1200MIPS compact DSP for multi-core media SoC	claim
28	140	A near optimal deblocking filter for H.264 advanced video coding	claim
29	137	Parameterized block-based non-gaussian statistical gate timing analysis	claim
30	135	Robust analytical gate delay modeling for low voltage circuits	claim
31	134	Constraint driven I/O planning and placement for chip-package co-design	claim
32	133	High-level architecture exploration for MPEG4 encoder with custom parameters	claim
33	133	High-throughput decoder for low-density parity-check code	claim
34	133	Crosstalk analysis using reconvergence correlation	claim
35	133	Monotonic parallel and orthogonal routing for single-layer ball grid array packages	claim
36	133	An SPU reference model for simulation, random test generation and verification	claim
37	131	POSIX modeling in SystemC	claim
38	130	Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops	claim
39	129	Yield-area optimizations of digital circuits using non-dominated sorting genetic algorithm (YOGA)	claim
40	129	Ultra-low voltage power management circuit and computation methodology for energy harvesting applications	claim
41	128	A new test and characterization scheme for 10+ GHz low jitter wide band PLL	claim
42	128	FastPlace 2.0: an efficient analytical placer for mixed-mode designs	claim
43	127	Memory size computation for multimedia processing applications	claim
44	126	PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures	claim
45	126	A novel instruction scratchpad memory optimization method based on concomitance metric	claim
46	125	ASIP approach for implementation of H.264/AVC	claim
47	125	Efficient identification of multi-cycle false path	claim
48	124	A built-in power supply noise probe for digital LSIs	claim
49	124	Functional modeling techniques for efficient SW code generation of video codec applications	claim
50	123	Implementation of H.264/AVC decoder for mobile video applications	claim
51	123	Efficient static timing analysis using a unified framework for false paths and multi-cycle paths	claim
52	122	IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults	claim
53	122	Reusable component IP design using refinement-based design environment	claim
54	121	A low dynamic power and low leakage power 90-nm CMOS square-root circuit	claim
55	121	Efficient early stage resonance estimation techniques for C4 package	claim
56	120	A novel framework for multilevel full-chip gridless routing	claim
57	120	Design space exploration for minimizing multi-project wafer production cost	claim
58	119	Using speculative computation and parallelizing techniques to improve scheduling of control based designs	claim
59	119	A dynamic test compaction procedure for high-quality path delay testing	claim
60	119	Configurable multi-processor architecture and its processor element design	claim
61	118	A probabilistic analysis of pipelined global interconnect under process variations	claim
62	118	Task placement heuristic based on 3D-adjacency and look-ahead in reconfigurable systems	claim
63	117	Signal-path driven partition and placement for analog circuit	claim
64	117	A memory grouping method for sharing memory BIST logic	claim
65	117	SAT-based optimal hypergraph partitioning with replication	claim
66	116	A robust detailed placement for mixed-size IC designs	claim
67	116	Post-routing redundant via insertion for yield/reliability improvement	claim
68	116	Abridged addressing: a low power memory addressing strategy	claim
69	116	Reducing dynamic compilation overhead by overlapping compilation and execution	claim
70	115	DraXRouter: global routing in X-Architecture with dynamic resource assignment	claim
71	115	Area optimization for leakage reduction and thermal stability in nanometer scale technologies	claim
72	115	Hardware implementation of super minimum all digital FM demodulator	claim
73	114	Yield-preferred via insertion based on novel geotopological technology	claim
74	114	High level equivalence symmetric input identification	claim
75	113	Transition-based coverage estimation for symbolic model checking	claim
76	112	Refinement strategies for verification methods based on datapath abstraction	claim
77	111	Lazy BTB: reduce BTB energy consumption using dynamic profiling	claim
78	111	Power distribution techniques for dual VDD circuits	claim
79	110	Switching-activity driven gate sizing and Vth assignment for low power design	claim
80	109	Cycle error correction in asynchronous clock modeling for cycle-based simulation	claim
81	109	Energy savings through embedded processing on disk system	claim
82	109	Adaptive admittance-based conductor meshing for interconnect analysis	claim
83	109	Hardware debugging method based on signal transitions and transactions	claim
84	108	Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems	claim
85	108	Spec-based flip-flop and latch repeater planning	claim
86	107	Energy-aware computation duplication for improving reliability in embedded chip multiprocessors	claim
87	107	Jitter decomposition in ring oscillators	claim
88	107	Delay variation tolerance for domino circuits	claim
89	106	Calculating frequency-dependent inductance of VLSI interconnect by complete multiple reciprocity boundary element method	claim
90	105	Speed binning aware design methodology to improve profit under parameter variations	claim
91	105	Maximizing data reuse for minimizing memory space requirements and execution cycles	claim
92	105	Improving routing efficiency for network-on-chip through contention-aware input selection	claim
93	104	Cache size selection for performance, energy and reliability of time-constrained systems	claim
94	104	A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers	claim
95	104	Configurability of performance and overheads in flash management	claim
96	104	Workload prediction and dynamic voltage scaling for MPEG decoding	claim
97	104	SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design	claim
98	103	Prefetching-aware cache line turnoff for saving leakage energy	claim
99	103	Memory optimal single appearance schedule with dynamic loop count for synchronous dataflow graphs	claim
100	103	Low area pipelined circuits by multi-clock cycle paths and clock scheduling	claim
101	102	Introduction to H.264 advanced video coding	claim
102	102	An O(mn) time algorithm for optimal buffer insertion of nets with m sinks	claim
103	101	An implementation of a CMOS down-conversion mixer for GSM1900 receiver	claim
104	101	Worst case execution time analysis for synthesized hardware	claim
105	100	Generation of shorter sequences for high resolution error diagnosis using sequential SAT	claim
106	99	Finding optimal L1 cache configuration for embedded systems	claim
107	99	Programmable numerical function generators based on quadratic approximation: architecture and synthesis method	claim
108	98	Word level functional coverage computation	claim
109	98	Timing-driven placement based on monotone cell ordering constraints	claim
110	97	Object duplication for improving reliability	claim
111	97	Fast multi-domain clock skew scheduling for peak current reduction	claim
112	97	SASIMI: sparsity-aware simulation of interconnect-dominated circuits with non-linear devices	claim
113	97	Wire sizing with scattering effect for nanoscale interconnection	claim
114	97	An unconditional stable general operator splitting method for transistor level transient analysis	claim
115	96	Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability	claim
116	95	Physical design implementation of segmented buses to reduce communication energy	claim
117	95	The design and implementation of a low-latency on-chip network	claim
118	95	A fast logic simulator using a look up table cascade emulator	claim
119	95	Simultaneous block and I/O buffer floorplanning for flip-chip design	claim
120	95	Interconnect RL extraction at a single representative frequency	claim
121	94	Mapping and configuration methods for multi-use-case networks on chips	claim
122	93	Open access overview "industrial experience"	claim
123	93	Electrothermal analysis and optimization techniques for nanoscale integrated circuits	claim
124	92	Adaptively-biased capacitor-less CMOS low dropout regulator with direct current feedback	claim
125	92	Double edge triggered Feedback Flip-Flop in sub 100NM technology	claim
126	92	Utility of the OpenAccess database in academic research	claim
127	92	Optimization of circuit trajectories: an auxiliary network approach	claim
128	92	An efficient algorithm for 3-D reluctance extraction considering high frequency effect	claim
129	91	Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs	claim
130	91	Statistical corner conditions of interconnect delay (corner LPE specifications)	claim
131	90	Design and implementation of transducer for ARM-TMS communication	claim
132	90	A routability constrained scan chain ordering technique for test power reduction	claim
133	90	A high-performance platform-based SoC for information security	claim
134	89	CGTA: current gain-based timing analysis for logic cells	claim
135	89	Co-synthesis of a configurable SoC platform based on a network on chip architecture	claim
136	88	Equivalent circuit modeling of guard ring structures for evaluation of substrate crosstalk isolation	claim
137	86	A 16-bit, low-power microsystem with monolithic MEMS-LC clocking	claim
138	84	Optimal topology exploration for application-specific 3D architectures	claim
139	84	Parasitics extraction involving 3-D conductors based on multi-layered Green's function	claim
140	83	FCSCAN: an efficient multiscan-based test compression technique for test cost reduction	claim
141	82	An exact algorithm for the statistical shortest path problem	claim
142	82	A transduction-based framework to synthesize RSFQ circuits	claim
143	82	Discovering the input assumptions in specification refinement coverage	claim
144	74	Macromodelling oscillators using Krylov-subspace methods	claim

Sciweavers

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers