26 search results - page 2 / 6 » A Performance Comparison of DRAM Memory System Optimizations... |
DSD
2010
IEEE
13 years 5 months ago
2010
IEEE
Abstract—Resizable caches can trade-off capacity for access speed to dynamically match the needs of the workload. In Simultaneous Multi-Threaded (SMT) cores, the caching needs ca...
MICRO
2009
IEEE
13 years 11 months ago
2009
IEEE
3D-integration is a promising technology to help combat the “Memory Wall” in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level...
ISCA
2010
IEEE
13 years 9 months ago
2010
IEEE
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
MICRO
1997
IEEE
13 years 9 months ago
1997
IEEE
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...
ISCA
2000
IEEE
13 years 9 months ago
2000
IEEE
The bandwidth and latency of a memory system are strongly dependent on the manner in which accesses interact with the “3-D” structure of banks, rows, and columns characteristi...