MICRO 1997 - PDF Preprint Papers

MICRO 1997 IEEE/ACM International Symposium on Microarchitecture

Teaser Browsing | Click Here

Title Browsing | Click Here

Wall of Fame | Most Viewed MICRO-1997 Paper

click to vote

MICRO
1997
IEEE

141views Hardware» more MICRO 1997»

Unroll-and-Jam Using Uniformly Generated Sets

13 years 9 months ago

Download www.cs.mtu.edu

Modern architectural trends in instruction-level parallelism (ILP) are to increase the computational power of microprocessors signiﬁcantly. As a result, the demands on memory ha...

Steve Carr, Yiping Guan

claim paper

Read More »

Disclaimer and Copyright Notice

Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.

Id	Views	Title	Status

1	141	Unroll-and-Jam Using Uniformly Generated Sets	claim
2	139	The Filter Cache: An Energy Efficient Memory Structure	claim
3	128	Run-Time Spatial Locality Detection and Optimization	claim
4	127	Exploiting Dead Value Information	claim
5	116	Tuning Compiler Optimizations for Simultaneous Multithreading	claim
6	110	The Design and Performance of a Conflict-Avoiding Cache	claim
7	108	Improving the Accuracy and Performance of Memory Communication Through Renaming	claim
8	105	The Multicluster Architecture: Reducing Cycle Time Through Partitioning	claim
9	93	A Comparison of Data Prefetching on an Access Decoupled and Superscalar Machine	claim
10	93	Trace Processors	claim
11	92	The Predictability of Data Values	claim
12	90	ProfileMe: Hardware Support for Instruction-Level Profiling on Out-of-Order Processors	claim
13	89	Available Parallelism in Video Applications	claim
14	87	Improving Code Density Using Compression Techniques	claim
15	86	Path-Based Next Trace Prediction	claim
16	86	Streamlining Inter-Operation Memory Communication via Data Dependence Prediction	claim
17	84	Procedure Placement Using Temporal Ordering Information	claim
18	82	Procedure Based Program Compression	claim
19	79	On High-Bandwidth Data Cache Design for Multi-Issue Processors	claim
20	76	A Framework for Balancing Control Flow and Predication	claim

Sciweavers

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers