204 search results - page 1 / 41 » A Pipelined Memory Architecture for High Throughput Network ... |
ISCA
2003
IEEE
13 years 11 months ago
2003
IEEE
Designing ASICs for each new generation of backbone routers is a time intensive and fiscally draining process. In this paper we focus on the design of a programmable architecture...
ISCA
2005
IEEE
13 years 12 months ago
2005
IEEE
Pipelined forwarding engines are used in core routers to meet speed demands. Tree-based searches are pipelined across a number of stages to achieve high throughput, but this resul...
MICRO
2006
IEEE
14 years 8 days ago
2006
IEEE
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
PDPTA
2003
13 years 7 months ago
2003
This paper investigates the protocol overhead pipelining between the host and network interface card (NIC). Existing researches into the protocol overhead pipelining assume that p...
MAM
2006
13 years 6 months ago
2006
Deep layer processing and increasing line rates present a memory challenge to processor