Sciweavers

204 search results - page 2 / 41
» A Pipelined Memory Architecture for High Throughput Network ...
Sort
View
ANCS
2006
ACM
13 years 11 months ago
CAMP: fast and efficient IP lookup architecture
A large body of research literature has focused on improving the performance of longest prefix match IP-lookup. More recently, embedded memory based architectures have been propos...
Sailesh Kumar, Michela Becchi, Patrick Crowley, Jo...
INFOCOM
2008
IEEE
13 years 11 months ago
Beyond TCAMs: An SRAM-Based Parallel Multi-Pipeline Architecture for Terabit IP Lookup
—Continuous growth in network link rates poses a strong demand on high speed IP lookup engines. While Ternary Content Addressable Memory (TCAM) based solutions serve most of toda...
Weirong Jiang, Qingbo Wang, Viktor K. Prasanna
HIPEAC
2007
Springer
13 years 11 months ago
A Throughput-Driven Task Creation and Mapping for Network Processors
Abstract. Network processors are programmable devices that can process packets at a high speed. A network processor is typified by multithreading and heterogeneous multiprocessing...
Lixia Liu, Xiao-Feng Li, Michael K. Chen, Roy Dz-C...
ICIP
2005
IEEE
14 years 7 months ago
High throughput 2D DCT/IDCT processor for video coding
This paper describes the architecture of an 8x8 2-D DCT/IDCT processor with high throughput, reduced hardware, and a parallel-pipeline scheme. This architecture allows the process...
Gustavo A. Ruiz, Juan A. Michell, Angel M. Buron
IPPS
2010
IEEE
13 years 3 months ago
Scalable multi-pipeline architecture for high performance multi-pattern string matching
Multi-pattern string matching remains a major performance bottleneck in network intrusion detection and anti-virus systems for high-speed deep packet inspection (DPI). Although Aho...
Weirong Jiang, Yi-Hua Edward Yang, Viktor K. Prasa...