High throughput 2D DCT/IDCT processor for video coding

14 years 6 months ago

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This paper describes the architecture of an 8x8 2-D DCT/IDCT processor with high throughput, reduced hardware, and a parallel-pipeline scheme. This architecture allows the processing elements and arithmetic units to work in parallel at half the frequency of the data input rate. A fully pipelined row-column decomposition method based on two 1-D DCTs and a transpose buffer based on D-type flip-flops are used. The processor has been implemented in a 0.35-?m CMOS process with a core area of 3mm2

Gustavo A. Ruiz, Juan A. Michell, Angel M. Buron

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