Sciweavers

204 search results - page 40 / 41
» A Pipelined Memory Architecture for High Throughput Network ...
Sort
View
CORR
2010
Springer
198views Education» more  CORR 2010»
13 years 6 months ago
Space and the Synchronic A-Ram
Space is a spatial programming language designed to exploit the massive parallelism available in a formal model of computation called the Synchronic A-Ram, and physically related ...
Alexander Victor Berka
IEEEPACT
2008
IEEE
14 years 12 days ago
Leveraging on-chip networks for data cache migration in chip multiprocessors
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that...
Noel Eisley, Li-Shiuan Peh, Li Shang
IJHPCA
2010
111views more  IJHPCA 2010»
13 years 3 months ago
Understanding Application Performance via Micro-benchmarks on Three Large Supercomputers: Intrepid, Ranger and Jaguar
Emergence of new parallel architectures presents new challenges for application developers. Supercomputers vary in processor speed, network topology, interconnect communication ch...
Abhinav Bhatele, Lukasz Wesolowski, Eric J. Bohm, ...
SIGMOD
2008
ACM
190views Database» more  SIGMOD 2008»
14 years 6 months ago
OLTP through the looking glass, and what we found there
Online Transaction Processing (OLTP) databases include a suite of features -- disk-resident B-trees and heap files, locking-based concurrency control, support for multi-threading ...
Stavros Harizopoulos, Daniel J. Abadi, Samuel Madd...
ICPP
2006
IEEE
14 years 19 hour ago
Data Transfers between Processes in an SMP System: Performance Study and Application to MPI
— This paper focuses on the transfer of large data in SMP systems. Achieving good performance for intranode communication is critical for developing an efficient communication s...
Darius Buntinas, Guillaume Mercier, William Gropp