7 search results - page 1 / 2 » A Power Estimation Model for High-Speed CMOS A D Converters |
DATE
1999
IEEE
13 years 9 months ago
1999
IEEE
Power estimation is important for system-level exploration and trade-off analysis of VLSI systems. A power estimator for high-speed analog to digital converters that exploits info...
DAC
1999
ACM
14 years 6 months ago
1999
ACM
A 550MHz 64b PowerPC processor was developed for fabrication in Silicon-On-Insulator (SOI) technology from a processor previously designed and fabricated in bulk CMOS [1]. Both th...
ISLPED
1995
ACM
13 years 8 months ago
1995
ACM
When estimating the dynamic power dissipated by a circuit di erent methods ranging from numeric analog simulation to event-driven logic simulation have been proposed. However, as ...
APCCAS
2002
IEEE
13 years 10 months ago
2002
IEEE
This paper presents a 10-bit pipeline ADC using double sampling technique to achieve a conversion rate of 40 MS/s at 2.5-V supply. The opamps are two-stage with folded-cascode as ...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...