8 search results - page 1 / 2 » A Practical Algorithm for Retiming Level-Clocked Circuits |
ICCD
1996
IEEE
13 years 9 months ago
1996
IEEE
ICCAD
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper describes a polynomial time algorithm for min-area retiming for edge-triggered circuits to handle both setup and hold constraints. Given a circuit G and a target clock ...
FPGA
1998
ACM
13 years 9 months ago
1998
ACM
In this paper, we present a new retiming-based technology mapping algorithm for look-up table-based eld programmable gate arrays. The algorithm is based on a novel iterative proce...
ISVLSI
2002
IEEE
13 years 10 months ago
2002
IEEE
Retiming has been shown to be a powerful technique for improving the performance of synchronous circuits. However, even though retiming algorithms of polynomial time complexity ha...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
—Optimizing sequential cycles is essential for many types of high-performance circuits, such as pipelines for packet processing. Retiming is a powerful technique for speeding pip...