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ISVLSI
2008
IEEE
173views VLSI» more  ISVLSI 2008»
13 years 11 months ago
Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques
The evolution of deep submicron technologies allows the development of increasingly complex Systems on a Chip (SoC). However, this evolution is rendering less viable some well-est...
Julian J. H. Pontes, Matheus T. Moreira, Rafael So...
IPPS
2005
IEEE
13 years 11 months ago
Practical Performance Model for Optimizing Dynamic Load Balancing of Adaptive Applications
Optimizing the performance of dynamic load balancing toolkits and applications requires the adjustment of several runtime parameters; however, determining sufficiently good value...
Kevin Barker, Nikos Chrisochoides
CIKM
1999
Springer
13 years 9 months ago
Mining Inter-Transaction Associations with Templates
Multi-dimensional, inter-transaction association rules extend the traditional association rules to describe more general associations among items with multiple properties cross tr...
Ling Feng, Hongjun Lu, Jeffrey Xu Yu, Jiawei Han
ICPADS
1998
IEEE
13 years 9 months ago
One-Phase Commit: Does it make Sense?
1 Although widely used in distributed transactional systems, the so-called Two-Phase Commit (2PC) protocol introduces a substantial delay in transaction processing, even in the abs...
Maha Abdallah, Rachid Guerraoui, Philippe Pucheral
CF
2004
ACM
13 years 10 months ago
Fault tolerant clockless wave pipeline design
This paper presents a fault tolerant design technique for the clockless wave pipeline. The specific architectural model investigated in this paper is the two-phase clockless asyn...
T. Feng, Byoungjae Jin, J. Wang, Nohpill Park, Yon...