Fault tolerant clockless wave pipeline design

This paper presents a fault tolerant design technique for the clockless wave pipeline. The specific architectural model investigated in this paper is the two-phase clockless asynchronous wave pipeline [10] which is ideally supposed to yield the theoretical maximum of performance. Request signal is the most critical component for the clockless-induced control of the wave pipelined processing of data. In practice, the request signal is very sensitive and vulnerable to electronic crosstalk noise, and this problem has become exteremely stringent for the ultra-high density integrated circuits today. Electronic noise may devastate the operational confidence level of the clockless wave pipeline. In this context, this paper characterizes the yield and reliability properties of the two-phase clockless asynchronous pipeline. Based on the yield characterization, a simple yet effective fault tolerance architecture and algorithm is proposed on the request signal lines as the most critical compon...

• Type: Conference
• Year: 2004
• Where: CF
• Authors: T. Feng, Byoungjae Jin, J. Wang, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi
• Keywords: CF 2004, Clockless Asynchronous Wave, Clockless Wave Pipeline, Wave Pipeline