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» A Probability-Based Approach to VLSI Circuit Partitioning
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VLSID
2003
IEEE
126views VLSI» more  VLSID 2003»
14 years 5 months ago
Comparison of Heuristic Algorithms for Variable Partitioning in Circuit Implementation
Functional decomposition is a process of splitting a complex circuit into smaller sub-circuits. This paper deals with the problem of determining the set of best free and bound var...
Muthukumar Venkatesan, Henry Selvaraj
EAAI
2007
103views more  EAAI 2007»
13 years 5 months ago
Particle swarm-based optimal partitioning algorithm for combinational CMOS circuits
This paper presents a swarm intelligence based approach to optimally partition combinational CMOS circuits for pseudoexhaustive testing. The partitioning algorithm ensures reducti...
Ganesh K. Venayagamoorthy, Scott C. Smith, Gaurav ...
DFT
2005
IEEE
64views VLSI» more  DFT 2005»
13 years 11 months ago
Implementation of Concurrent Checking Circuits by Independent Sub-circuits
The present paper proposes a new method for detecting arbitrary faults in a functional circuit when the set of codewords is limited and known in advance. The method is based on im...
Vladimir Ostrovsky, Ilya Levin
VLSID
2003
IEEE
167views VLSI» more  VLSID 2003»
14 years 5 months ago
Timing Minimization by Statistical Timing hMetis-based Partitioning
In this paper we present statistical timing driven hMetisbased partitioning. We approach timing driven partitioning from a different perspective: we use the statistical timing cri...
Cristinel Ababei, Kia Bazargan
VLSID
2001
IEEE
129views VLSI» more  VLSID 2001»
14 years 5 months ago
Design Of Provably Correct Storage Arrays
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann