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» A Reliable Hardware Barrier Synchronization Scheme
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ICCD
1996
IEEE
134views Hardware» more  ICCD 1996»
13 years 9 months ago
Pausible Clocking: A First Step Toward Heterogeneous Systems
This paper describes a novel communication scheme, which is guaranteed to be free of synchronization failures, amongst multiple synchronous modules operating independently. In thi...
Kenneth Y. Yun, Ryan P. Donohue
ASYNC
2002
IEEE
115views Hardware» more  ASYNC 2002»
13 years 10 months ago
Point to Point GALS Interconnect
Reliable, low-latency channel communication between independent clock domains may be achieved using a combination of clock pausing techniques, self-calibrating delay lines and an ...
George S. Taylor, Simon W. Moore, Robert D. Mullin...
ECBS
2009
IEEE
164views Hardware» more  ECBS 2009»
14 years 5 days ago
Semantically Enhanced Containers for Concurrent Real-Time Systems
Future space missions, such as Mars Science Laboratory, are built upon computing platforms providing a high degree of autonomy and diverse functionality. The increased sophisticat...
Damian Dechev, Peter Pirkelbauer, Nicolas Rouquett...