20 search results - page 1 / 4 » A Scheduling Method for Synchronous Communication in the Bac... |
ASPDAC
1999
ACM
13 years 9 months ago
1999
ACM
− In this paper, we propose a scheduling method for synchronous communication between threads in the Bach hardware compiler. In this method, all communications are extracted from...
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
—Synchronous languages offer a deterministic model of concurrency at the level of actions. However, essentially all compilers for synchronous languages compile these actions into...
ICCD
1993
IEEE
13 years 9 months ago
1993
IEEE
Ravel-XL is a single-boardhardware accelerator for gate-level digital logic simulation. It uses a standard levelizedcode approach to statically schedule gate evaluations.However, u...
MICRO
2010
IEEE
13 years 3 months ago
2010
IEEE
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
MEMOCODE
2003
IEEE
13 years 10 months ago
2003
IEEE
System-level design methodologies for embedded HW/SW systems face several challenges: In order to be susceptible to systematic formal analysis based on state-space exploration, a ...