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» A Sequential Reduction Strategy
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DAC
1996
ACM
13 years 10 months ago
Desensitization for Power Reduction in Sequential Circuits
In this paper, we describe a technique for power reduction in sequential circuits. Existing signals in the circuit are used to selectively disable some of the registers so that a ...
Xiangfeng Chen, Peichen Pan, C. L. Liu
PR
2007
129views more  PR 2007»
13 years 5 months ago
EROS: Ensemble rough subspaces
Ensemble learning is attracting much attention from pattern recognition and machine learning domains for good generalization. Both theoretical and experimental researches show tha...
Qinghua Hu, Daren Yu, Zongxia Xie, Xiaodong Li
DFT
2007
IEEE
104views VLSI» more  DFT 2007»
14 years 9 days ago
Reduction of Fault Latency in Sequential Circuits by using Decomposition
The paper discusses a novel approach for reduction of fault detection latency in a selfchecking sequential circuit. The Authors propose decomposing the finite state machine (FSM) ...
Ilya Levin, Benjamin Abramov, Vladimir Ostrovsky
ISQED
2007
IEEE
135views Hardware» more  ISQED 2007»
14 years 7 days ago
MARS-S: Modeling and Reduction of Soft Errors in Sequential Circuits
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we use...
Natasa Miskov-Zivanov, Diana Marculescu
DMIN
2006
108views Data Mining» more  DMIN 2006»
13 years 7 months ago
Sequential and Parallel Rule Extraction from a Concept Lattice
This paper presents enhancements to previous algorithms for the sequential extraction of complete non-redundant set of rules from a concept lattice. The aim of these enhancements i...
Guillermo Tonsmann