DFT 2007 - PDF Preprint Papers

DFT 2007 IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems

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DFT
2007
IEEE

152views VLSI» more DFT 2007»

TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs

13 years 9 months ago

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This paper presents the adoption of the Triple Modular Redundancy coupled with the Partial Dynamic Reconfiguration of Field Programmable Gate Arrays to mitigate the effects of Sof...

Cristiana Bolchini, Antonio Miele, Marco D. Santam...

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Id	Views	Title	Status

1	152	TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs	claim
2	142	Quantitative Analysis of In-Field Defects in Image Sensor Arrays	claim
3	141	A Fault-Tolerant Active Pixel Sensor to Correct In-Field Hot Pixel Defects	claim
4	135	Fault Secure Encoder and Decoder for Memory Applications	claim
5	123	Checker Design for On-line Testing of Xilinx FPGA Communication Protocols	claim
6	112	Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model	claim
7	109	Safety Evaluation of NanoFabrics	claim
8	105	A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction	claim
9	104	Reduction of Fault Latency in Sequential Circuits by using Decomposition	claim
10	103	Lazy Error Detection for Microprocessor Functional Units	claim
11	103	Reliable Network-on-Chip Using a Low Cost Unequal Error Protection Code	claim
12	101	Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits	claim
13	100	Soft Error Hardening for Asynchronous Circuits	claim
14	95	Fault Tolerant Source Routing for Network-on-Chip	claim
15	86	Production Yield and Self-Configuration in the Future Massively Defective Nanochips	claim
16	86	Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines	claim

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