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FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
13 years 5 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
VEE
2010
ACM
218views Virtualization» more  VEE 2010»
14 years 8 days ago
Improving compiler-runtime separation with XIR
Intense research on virtual machines has highlighted the need for flexible software architectures that allow quick evaluation of new design and implementation techniques. The inte...
Ben Titzer, Thomas Würthinger, Doug Simon, Ma...
MICRO
1997
IEEE
116views Hardware» more  MICRO 1997»
13 years 9 months ago
Tuning Compiler Optimizations for Simultaneous Multithreading
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...
Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay ...
PLDI
2009
ACM
14 years 6 months ago
Automatic generation of library bindings using static analysis
High-level languages are growing in popularity. However, decades of C software development have produced large libraries of fast, timetested, meritorious code that are impractical...
Tristan Ravitch, Steve Jackson, Eric Aderhold, Ben...
FDL
2003
IEEE
13 years 10 months ago
Object-Oriented ASIP Design and Synthesis
SystemC-Plus from the ODETTE project provides the ability to simulate and synthesise object-oriented specifications into hardware. The current ODETTE compiler translates each obj...
Maziar Goudarzi, Shaahin Hessabi, Alan Mycroft