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» A Study of Energy Saving in Customizable Processors
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CLUSTER
2005
IEEE
13 years 10 months ago
A Feasibility Analysis of Power Awareness in Commodity-Based High-Performance Clusters
We present a feasibility study of a power-reduction scheme that reduces the thermal power of processors by lowering frequency and voltage in the context of high-performance comput...
Chung-Hsing Hsu, Wu-chun Feng
SIGMETRICS
2012
ACM
290views Hardware» more  SIGMETRICS 2012»
11 years 7 months ago
Power and energy containers for multicore servers
Energy efficiency and power capping remain growing concerns in server systems. Online applications continue to evolve with new features and dynamic clientdirected processing, res...
Kai Shen, Arrvindh Shriraman, Sandhya Dwarkadas, X...
PDP
2010
IEEE
13 years 9 months ago
Energy-Efficient Hardware Prefetching for CMPs Using Heterogeneous Interconnects
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
Antonio Flores, Juan L. Aragón, Manuel E. A...
ISLPED
2000
ACM
77views Hardware» more  ISLPED 2000»
13 years 9 months ago
A recursive algorithm for low-power memory partitioning
Memory-processor integration o ers new opportunities for reducing the energy of a system. In the case of embedded systems, one solution consists of mapping the most frequently acc...
Luca Benini, Alberto Macii, Massimo Poncino
DSD
2007
IEEE
132views Hardware» more  DSD 2007»
13 years 9 months ago
On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology
In this study, we investigate different cache fault tolerance techniques to determine which will be most effective when on-chip memory cell defect probabilities exceed those of cu...
David Roberts, Nam Sung Kim, Trevor N. Mudge