In this paper, we propose a new hardware unit that performs a 16 × 1 SAD operation. The hardware unit is intended to augment a general-purpose core. Further, we show that the 16 ...
Stephan Wong, Stamatis Vassiliadis, Sorin Cotofana
Molecular Dynamics simulations have become an interesting target for acceleration using Field-Programmable Gate Arrays (FPGA). Still to be attempted completely in FPGA hardware is...
This paper presents high-throughput techniques for implementing FSM based string matching hardware on FPGAs. By taking advantage of the fact that string matching operations for di...
Atul Mahajan, Benfano Soewito, Sai K. Parsi, Ning ...
Abstract— In this paper, we propose partly parallel architectures based on optimal overlapped sum-product (OSP) decoding. To ensure high throughput and hardware utilization effi...
The first successful FPGA implementation [1] of artificial neural networks (ANNs) was published a little over a decade ago. It is timely to review the progress that has been made i...