12 search results - page 1 / 3 » A Temporal Assertion Extension to Verilog |
ATVA
2004
Springer
13 years 10 months ago
2004
Springer
Many circuit designs need to follow some temporal rules. However, it is hard to express and verify them in the past. Therefore, a temporal assertion extension to Verilog, called Te...
ICALP
2009
Springer
14 years 5 months ago
2009
Springer
The IEEE standardized Property Specification Language, PSL for short, extends the well-known linear-time temporal logic LTL with so-called semi-extended regular expressions. PSL an...
ACTA
2010
13 years 5 months ago
2010
The IEEE standardized Property Specification Language, PSL for short, extends the well-known linear-time temporal logic LTL with so-called semi-extended regular expressions. PSL an...
FMCAD
2008
Springer
13 years 6 months ago
2008
Springer
The semantics of temporal logic is usually defined with respect to a word representing a computation path over a set of atomic propositions. A temporal logic formula does not contr...
SPIN
2000
Springer
13 years 8 months ago
2000
Springer
The Temporal Rover is a specification based verification tool for applications written in C, C++, Java, Verilog and VHDL. The tool combines formal specification, using Linear-Time ...