264 search results - page 51 / 53 » A Time Predictable Instruction Cache for a Java Processor |
HPCA
2003
IEEE
14 years 6 months ago
2003
IEEE
Although caches for decades have been the backbone of the memory system, the speed gap between CPU and main memory suggests their augmentation with prefetching mechanisms. Recentl...
ECRTS
2007
IEEE
14 years 3 days ago
2007
IEEE
Many embedded systems feature processors coupled with a small and fast scratchpad memory. To the difference with caches, allocation of data to scratchpad memory must be handled by...
RTSS
2007
IEEE
14 years 1 days ago
2007
IEEE
In this paper, we propose to implement hybrid operating systems based on two-level hardware interrupts. To separate real-time and non-real-time hardware interrupts by hardware, we...
IEEEPACT
2005
IEEE
13 years 11 months ago
2005
IEEE
Scratchpad memory (SPM), a fast software-managed onchip SRAM, is now widely used in modern embedded processors. Compared to hardware-managed cache, it is more efficient in perfor...
ASPLOS
2004
ACM
13 years 11 months ago
2004
ACM
This paper introduces a compiler-orchestrated prefetching system as a unified framework geared toward ameliorating the gap between processing speeds and memory access latencies. ...