3955 search results - page 2 / 791 » A Transactional Architecture for Simulation |
HPCA
2005
IEEE
14 years 5 months ago
2005
IEEE
Hardware transactional memory should support unbounded transactions: transactions of arbitrary size and duration. We describe a hardware implementation of unbounded transactional ...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
The concept of a SOC platform architecture introduces the concept of a communication infrastructure. In the transaction-level a finite set of architecture components (memories, ar...
DATE
2005
IEEE
13 years 7 months ago
2005
IEEE
Transaction Level Modeling (TLM) approach is used to meet the simulation speed as well as cycle accuracy for large scale SoC performance analysis. We implemented a transaction-lev...
ISCA
1993
IEEE
13 years 9 months ago
1993
IEEE
A shared data structure is lock-free if its operations do not require mutual exclusion. If one process is interrupted in the middle of an operation, other processes will not be pr...
ISQED
2006
IEEE
13 years 11 months ago
2006
IEEE
System on Chip architectures have traditionally relied upon bus based interconnect for their communication needs. However, increasing bus frequencies and the load on the bus calls...