ISQED 2006 - PDF Preprint Papers

ISQED 2006 International Symposium on Quality Electronic Design

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ISQED
2006
IEEE

259views Hardware» more ISQED 2006»

Impact of NBTI on SRAM Read Stability and Design for Reliability

13 years 10 months ago

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— Negative Bias Temperature Instability (NBTI) has the potential to become one of the main show-stoppers of circuit reliability in nanometer scale devices due to its deleterious ...

Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatneka...

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Id	Views	Title	Status

1	259	Impact of NBTI on SRAM Read Stability and Design for Reliability	claim
2	176	Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages	claim
3	172	Future Memory Technology Trends and Challenges	claim
4	155	FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs	claim
5	153	Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO)	claim
6	147	Compact Reduced Order Modeling for Multiple-Port Interconnects	claim
7	142	Constructing Current-Based Gate Models Based on Existing Timing Library	claim
8	136	An Improved AMG-based Method for Fast Power Grid Analysis	claim
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10	126	Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity	claim
11	124	DFM Metrics for Standard Cells	claim
12	123	A Simulation-Based Soft Error Estimation Methodology for Computer Systems	claim
13	118	Design of a Single Event Upset (SEU) Mitigation Technique for Programmable Devices	claim
14	118	Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming	claim
15	118	Language-Based High Level Transaction Extraction on On-chip Buses	claim
16	116	Probabilistic Delay Budgeting for Soft Realtime Applications	claim
17	109	Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective	claim
18	108	SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching	claim
19	107	On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design	claim
20	107	Impact of Gate-Length Biasing on Threshold-Voltage Selection	claim
21	106	Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration	claim
22	103	Efficient Model Update for General Link-Insertion Networks	claim
23	101	Compiler-Directed Power Density Reduction in NoC-Based Multi-Core Designs	claim
24	100	Simplicity and Executability: Cornerstones of Quality	claim
25	97	Device and Technology Challenges for Nanoscale CMOS	claim
26	94	System-Level SRAM Yield Enhancement	claim
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29	90	Monte Carlo-Alternative Probabilistic Simulations for Analog Systems	claim
30	89	Study of Floating Fill Impact on Interconnect Capacitance	claim
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34	75	Interconnect and Thermal-aware Floorplanning for 3D Microprocessors	claim
35	69	Statistical Analysis of Capacitance Coupling Effects on Delay and Noise	claim

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