7 search results - page 2 / 2 » A Two-State Methodology for RTL Logic Simulation |
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
- Power consumption is one of the major challenges in VLSI Design. Power constrained designs need tools to accurately predict the power consumption and provide feedback to designer...
ISSS
2002
IEEE
13 years 10 months ago
2002
IEEE
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...