23 search results - page 2 / 5 » A Unified Compressed Memory Hierarchy |
CGO
2003
IEEE
13 years 9 months ago
2003
IEEE
In this paper, we present METRIC, an environment for determining memory inefficiencies by examining data traces. METRIC is designed to alter the performance behavior of applicatio...
ISLPED
2005
ACM
13 years 11 months ago
2005
ACM
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
PLDI
1995
ACM
13 years 9 months ago
1995
ACM
We present a unified approach to locality optimization that employs both data and control transformations. Data transformations include changing the array layout in memory. Contr...
WMPI
2004
ACM
13 years 10 months ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
TVLSI
2010
13 years 20 hour ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...