31 search results - page 1 / 7 » A Unified Framework for the Formal Verification of Sequentia... |
ICCAD
1990
IEEE
13 years 9 months ago
1990
IEEE
ICCAD
2002
IEEE
14 years 2 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
CAV
2010
Springer
13 years 5 months ago
2010
Springer
ABC is a public-domain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transforma...
ECAI
2006
Springer
13 years 9 months ago
2006
Springer
Several formalisms exist to express and solve decision problems. Each is designed to capture different kinds of knowledge: utilities expressing preferences, uncertainties on the en...
CCECE
2006
IEEE
13 years 11 months ago
2006
IEEE
To help programmers of high-performance computing (HPC) systems avoid communication-related errors, we employ a formal process algebra, Communicating Sequential Processes (CSP), w...