12 search results - page 2 / 3 » A Verilog RTL Synthesis Tool for Heterogeneous FPGAs |
LCTRTS
2007
Springer
13 years 12 months ago
2007
Springer
This paper presents a tool for automatic synthesis of RTL interfaces for heterogeneous MPSoC from transaction level models (TLMs). The tool captures the communication parameters i...
ASPDAC
2012
ACM
12 years 1 months ago
2012
ACM
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
CODES
2005
IEEE
13 years 11 months ago
2005
IEEE
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
FPL
1999
Springer
13 years 10 months ago
1999
Springer
Abstract. High-performance design flows for FPGAs often rely on module generators to counter coarse logic-block granularity and limited routing resources, However, the very flexi...
SAMOS
2007
Springer
13 years 12 months ago
2007
Springer
—This paper presents a new methodology based on evolutionary multi-objective optimization (EMO) to synthesize multiple complex modules on programmable devices (FPGAs). It starts ...