70 search results - page 14 / 14 » A Virtual Memory Model for Parallel Supercomputers |
MICRO
2010
IEEE
13 years 3 months ago
2010
IEEE
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
ISCA
1996
IEEE
13 years 9 months ago
1996
IEEE
In an effort to push the envelope of system performance, microprocessor designs are continually exploiting higher levels of instruction-level parallelism, resulting in increasing ...
OOPSLA
2010
Springer
13 years 3 months ago
2010
Springer
Heterogeneous multi-core processors, such as the IBM Cell processor, can deliver high performance. However, these processors are notoriously difficult to program: different cores...
ISLPED
2004
ACM
13 years 10 months ago
2004
ACM
While set-associative caches incur fewer misses than directmapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are p...
ASPLOS
2006
ACM
13 years 8 months ago
2006
ACM
This paper proposes new network interface controller (NIC) designs that take advantage of integration with the host CPU to provide increased flexibility for operating system kerne...