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» A batch scheduler with high level components
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ISLPED
2003
ACM
155views Hardware» more  ISLPED 2003»
13 years 10 months ago
Low-power high-level synthesis for FPGA architectures
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
Deming Chen, Jason Cong, Yiping Fan
ICCAD
1993
IEEE
104views Hardware» more  ICCAD 1993»
13 years 9 months ago
Parallel timing simulation on a distributed memory multiprocessor
Circuit simulation is one of the most computationally expensive tasks in circuit design and optimization. Detailed simulation at the level of precision of SPICE is usually perform...
Chih-Po Wen, Katherine A. Yelick
IPPS
2002
IEEE
13 years 10 months ago
Performance Prediction Technology for Agent-Based Resource Management in Grid Environments
Resource management constitutes an important infrastructural component of a computational grid environment. The aim of grid resource management is to efficiently schedule applicat...
Junwei Cao, Stephen A. Jarvis, Daniel P. Spooner, ...
WSC
2008
13 years 7 months ago
Distributed agent-based simulation of construction projects with HLA
Simulation techniques can provide a resource-driven schedule and answer many hypothetical scenarios before project execution to improve on conventional project management software...
Hosein Taghaddos, Simaan M. AbouRizk, Yasser Moham...
PVLDB
2010
139views more  PVLDB 2010»
13 years 3 months ago
Aether: A Scalable Approach to Logging
The shift to multi-core hardware brings new challenges to database systems, as the software parallelism determines performance. Even though database systems traditionally accommod...
Ryan Johnson, Ippokratis Pandis, Radu Stoica, Mano...