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CORR
2008
Springer
104views Education» more  CORR 2008»
13 years 5 months ago
Policies of System Level Pipeline Modeling
Pipelining is a well understood and often used implementation technique for increasing the performance of a hardware system. We develop several SystemC/C++ modeling techniques tha...
Edwin A. Harcourt
DATE
2005
IEEE
154views Hardware» more  DATE 2005»
13 years 10 months ago
A Time Slice Based Scheduler Model for System Level Design
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...
Luciano Lavagno, Claudio Passerone, Vishal Shah, Y...
AHS
2007
IEEE
251views Hardware» more  AHS 2007»
13 years 9 months ago
System Level Modelling of Reconfigurable FFT Architecture for System-on-Chip Design
In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity...
Ali Ahmadinia, Balal Ahmad, Tughrul Arslan
CODES
2010
IEEE
13 years 3 months ago
Statistical approach in a system level methodology to deal with process variation
The impact of process variation in state of the art technology makes traditional (worst case) designs unnecessarily pessimistic, which translates to suboptimal designs in terms of...
Concepción Sanz Pineda, Manuel Prieto, Jos&...
HPCA
2008
IEEE
14 years 5 months ago
System level analysis of fast, per-core DVFS using on-chip switching regulators
Portable, embedded systems place ever-increasing demands on high-performance, low-power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a well-known techniq...
Wonyoung Kim, Meeta Sharma Gupta, Gu-Yeon Wei, Dav...