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ISCA
2010
IEEE
199views Hardware» more  ISCA 2010»
13 years 9 months ago
A case for FAME: FPGA architecture model execution
Given the multicore microprocessor revolution, we argue that the architecture research community needs a dramatic increase in simulation capacity. We believe FPGA Architecture Mod...
Zhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bi...
WETICE
1998
IEEE
13 years 9 months ago
A Framework for Adaptive Process Modeling and Execution (FAME)
This paper describes the architecture and concept of operation of a Framework for Adaptive Process Modeling and Execution (FAME). The research addresses the absence of robust meth...
Perakath C. Benjamin, Madhav Erraguntla, Richard J...
CASES
2009
ACM
13 years 11 months ago
CheckerCore: enhancing an FPGA soft core to capture worst-case execution times
Embedded processors have become increasingly complex, resulting in variable execution behavior and reduced timing predictability. On such processors, safe timing specifications e...
Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Ta...
VLSI
2012
Springer
12 years 14 days ago
A Signature-Based Power Model for MPSoC on FPGA
e technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used instruction-set sim...
Roberta Piscitelli, Andy D. Pimentel
APCSAC
2005
IEEE
13 years 10 months ago
A Stream Architecture Supporting Multiple Stream Execution Models
Multimedia devices demands a platform integrated various functional modules and an increasing support of multiple standards. Stream architecture is able to solve the problem. Howev...
Nan Wu, Mei Wen, Haiyan Li, Li Li, Chunyuan Zhang