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IPPS
1997
IEEE
13 years 10 months ago
A Reliable Hardware Barrier Synchronization Scheme
Barrier synchronization is a crucial operation for parallel systems. Many schemes have been proposed in the literature to achieve fast barrier synchronization through software, ha...
Rajeev Sivaram, Craig B. Stunkel, Dhabaleswar K. P...
SOSP
1997
ACM
13 years 7 months ago
Cashmere-2L: Software Coherent Shared Memory on a Clustered Remote-Write Network
Low-latency remote-write networks, such as DEC’s Memory Channel, provide the possibility of transparent, inexpensive, large-scale shared-memory parallel computing on clusters of...
Robert Stets, Sandhya Dwarkadas, Nikos Hardavellas...
DAC
2002
ACM
14 years 7 months ago
Software synthesis from synchronous specifications using logic simulation techniques
This paper addresses the problem of automatic generation of implementation software from high-level functional specifications in the context of embedded system on chip designs. So...
Yunjian Jiang, Robert K. Brayton
CGO
2004
IEEE
13 years 9 months ago
Compiler Optimization of Memory-Resident Value Communication Between Speculative Threads
Efficient inter-thread value communication is essential for improving performance in Thread-Level Speculation (TLS). Although several mechanisms for improving value communication ...
Antonia Zhai, Christopher B. Colohan, J. Gregory S...
HPCA
1999
IEEE
13 years 10 months ago
Comparative Evaluation of Fine- and Coarse-Grain Approaches for Software Distributed Shared Memory
Symmetric multiprocessors (SMPs) connected with low-latency networks provide attractive building blocks for software distributed shared memory systems. Two distinct approaches hav...
Sandhya Dwarkadas, Kourosh Gharachorloo, Leonidas ...