88 search results - page 2 / 18 » A code-generator generator for multi-output instructions |
ASPDAC
2004
ACM
13 years 10 months ago
2004
ACM
ISSS
1997
IEEE
13 years 9 months ago
1997
IEEE
This paper presents a model for simultaneous instruction selection, compaction, and register allocation. An arc mapping model along with logical propositions is used to create an ...
ENTCS
2002
13 years 4 months ago
2002
Digital signal processors provide specialized SIMD (single instruction multiple data) operations designed to dramatically increase performance in embedded systems. While these ope...
ISSS
1995
IEEE
13 years 8 months ago
1995
IEEE
This paper examines the problem of code-generation for expression trees on non-homogeneous register set architectures. It proposes and proves the optimality of an O(n) algorithm f...
MICRO
1992
IEEE
13 years 8 months ago
1992
IEEE
Software pipelining is an important instruction scheduling technique for efficiently overlapping successive iterations of loops and executing them in parallel. Modulo scheduling i...