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11

ISSS
1997
IEEE

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An Efficient Model for DSP Code Generation: Performance, Code Size, Estimated Energy

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An Efficient Model for DSP Code Generation: Performance, Code Size, Estimated Energy

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This paper presents a model for simultaneous instruction selection, compaction, and register allocation. An arc mapping model along with logical propositions is used to create an optimization model. Code is generated in fast cpu times and is optimized for minimum code size, maximum performance or estimated energy dissipation. Code generated for realistic DSP applications provide perfor

Catherine H. Gebotys

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Arc Mapping Model | Hardware | ISSS 1997 | Minimum Code Size | Simultaneous Instruction Selection |

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Added	06 Aug 2010
Updated	06 Aug 2010
Type	Conference
Year	1997
Where	ISSS
Authors	Catherine H. Gebotys

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