11 search results - page 2 / 3 » A codesigned on-chip logic minimizer |
CODES
2003
IEEE
13 years 10 months ago
2003
IEEE
Boolean logic minimization is traditionally used in logic synthesis tools running on powerful desktop computers. However, logic minimization has recently been proposed for dynamic...
DAC
2004
ACM
14 years 6 months ago
2004
ACM
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
ISQED
2007
IEEE
13 years 11 months ago
2007
IEEE
Straining of silicon improves mobility of carriers resulting in speed enhancement for transistors in CMOS technology. Traditionally, silicon straining is applied in a similar ad-h...
DAC
1999
ACM
14 years 6 months ago
1999
ACM
Partitioning and clustering are crucial steps in circuit layout for handling large scale designs enabled by the deep submicron technologies. Retiming is an important sequential lo...
FPL
1998
Springer
13 years 9 months ago
1998
Springer
The readily available performance advantages, gained in early virtual circuitry systems, are being recouped following advances in general purpose processor architectures and have ...