5 search results - page 1 / 1 » A communication characterisation of Splash-2 and Parsec |
IISWC
2009
IEEE
13 years 11 months ago
2009
IEEE
Recent benchmark suite releases such as Parsec specifically utilise the tightly coupled cores available in chipmultiprocessors to allow the use of newer, high performance, models ...
MICRO
2010
IEEE
13 years 2 months ago
2010
IEEE
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for ...
HOTI
2011
IEEE
12 years 4 months ago
2011
IEEE
Abstract—Network-on-Chips (NoCs) paradigm is fast becoming a defacto standard for designing communication infrastructure for multicores with the dual goals of reducing power cons...
ASPLOS
2010
ACM
13 years 11 months ago
2010
ACM
The behavior of a multithreaded program does not depend only on its inputs. Scheduling, memory reordering, timing, and low-level hardware effects all introduce nondeterminism in t...
MICRO
2009
IEEE
13 years 11 months ago
2009
IEEE
Hardware support for dynamic analysis can minimize the performance overhead of useful applications such as security checks, debugging, and profiling. To eliminate implementation ...