13 search results - page 1 / 3 » A cycle-accurate compilation algorithm for custom pipelined ... |
CODES
2005
IEEE
13 years 10 months ago
2005
IEEE
ESTIMEDIA
2005
Springer
13 years 10 months ago
2005
Springer
Designing Application-Specific Instruction-set Processors (ASIPs) usually requires designing a custom datapath, and modifying instruction-set, instruction decoder, and compiler. A...
ICCAD
2001
IEEE
14 years 1 months ago
2001
IEEE
In this paper we describe a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW proc...
CGO
2008
IEEE
13 years 11 months ago
2008
IEEE
In the embedded domain, custom hardware in the form of ASICs is often used to implement critical parts of applications when performance and energy efficiency goals cannot be met ...
DAC
2004
ACM
13 years 10 months ago
2004
ACM
Silicon compilers are often used in conjunction with Field Programmable Gate Arrays (FPGAs) to deliver flexibility, fast prototyping, and accelerated time-to-market. Many of these...