100 search results - page 3 / 20 » A decoupled KILO-instruction processor |
CONPAR
1992
13 years 10 months ago
1992
The Asynchronous Polycyclic Architecture (APA) is a new processor design for numerically intensive applications. APA resembles the VLIW architecture, in that it provides independen...
HPCA
2006
IEEE
14 years 6 months ago
2006
IEEE
Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elu...
HPCA
2000
IEEE
13 years 10 months ago
2000
IEEE
Value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction, and executes speculatively its data-dependent instructions based on ...
ISCA
1999
IEEE
13 years 10 months ago
1999
IEEE
Providing adequate data bandwidth is extremely important for a wide-issue superscalar processor to achieve its full performance potential. Adding a large number of ports to a data...
ASPDAC
2005
ACM
13 years 7 months ago
2005
ACM
— On current superscalar processors, performance and power issues cannot be decoupled for designers. Extensive simulations are usually required to meet both power and performance...