65 search results - page 12 / 13 » A delay model for logic synthesis of continuously-sized netw... |
ISCA
2007
IEEE
14 years 11 days ago
2007
IEEE
The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposal...
SSD
2005
Springer
13 years 11 months ago
2005
Springer
Networks often form the core of many users’ spatial databases. Networks are used to support the rapid navigation and analysis of linearly connected data such as that found in tra...
ISPASS
2009
IEEE
14 years 26 days ago
2009
IEEE
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
GECCO
2004
Springer
13 years 11 months ago
2004
Springer
Hybrid algorithms that combine genetic algorithms with the Nelder-Mead simplex algorithm have been effective in solving certain optimization problems. In this article, we apply a s...
ICCAD
2005
IEEE
14 years 3 months ago
2005
IEEE
In this paper we present NoCEE, a fast and accurate method for extracting energy models for packet-switched Network on Chip (NoC) routers. Linear regression is used to model the r...