ISCA 2007 - PDF Preprint Papers

ISCA 2007 International Symposium on Computer Architecture

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ISCA
2007
IEEE

217views Hardware» more ISCA 2007»

Parallel Processing of High-Dimensional Remote Sensing Images Using Cluster Computer Architectures

13 years 5 months ago

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Hyperspectral sensors represent the most advanced instruments currently available for remote sensing of the Earth. The high spatial and spectral resolution of the images supplied ...

David Valencia, Antonio Plaza, Pablo Martín...

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Id	Views	Title	Status

1	217	Parallel Processing of High-Dimensional Remote Sensing Images Using Cluster Computer Architectures	claim
2	208	Core fusion: accommodating software diversity in chip multiprocessors	claim
3	198	Making the fast case common and the uncommon case simple in unbounded transactional memory	claim
4	196	Anton, a special-purpose machine for molecular dynamics simulation	claim
5	192	Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite	claim
6	182	Configurable isolation: building high availability systems with commodity multi-core processors	claim
7	177	Adaptive insertion policies for high performance caching	claim
8	174	An integrated hardware-software approach to flexible transactional memory	claim
9	171	Power provisioning for a warehouse-sized computer	claim
10	168	Limiting the power consumption of main memory	claim
11	167	New cache designs for thwarting software cache-based side channel attacks	claim
12	162	BulkSC: bulk enforcement of sequential consistency	claim
13	161	Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors	claim
14	152	Carbon: architectural support for fine-grained parallelism on chip multiprocessors	claim
15	149	Virtual private caches	claim
16	149	An effective hybrid transactional memory system with strong isolation guarantees	claim
17	146	Hardware atomicity for reliable software speculation	claim
18	146	Virtual hierarchies to support server consolidation	claim
19	146	Automated design of application specific superscalar processors: an analytical approach	claim
20	145	Mechanisms for store-wait-free multiprocessors	claim
21	143	Interconnect design considerations for large NUCA caches	claim
22	143	Performance pathologies in hardware transactional memory	claim
23	142	MetaTM//TxLinux: transactional memory for an operating system	claim
24	130	Dynamic prediction of architectural vulnerability from microarchitectural state	claim
25	130	Non-Inclusion Property in Multi-Level Caches Revisited	claim
26	128	Performance and security lessons learned from virtualizing the alpha processor	claim
27	126	Comparing memory systems for chip multiprocessors	claim
28	120	Examining ACE analysis reliability estimates using fault-injection	claim
29	117	ReCycle: : pipeline adaptation to tolerate process variation	claim
30	116	A 64-bit stream processor architecture for scientific applications	claim
31	115	VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization	claim
32	114	Mechanisms for bounding vulnerabilities of processor structures	claim
33	114	Matrix scheduler reloaded	claim
34	113	Thermal modeling and management of DRAM memory systems	claim
35	111	Express virtual channels: towards the ideal interconnection fabric	claim
36	110	Late-binding: enabling unordered load-store queues	claim
37	110	A novel dimensionally-decomposed router for on-chip communication in 3D architectures	claim
38	109	Raksha: a flexible information flow architecture for software security	claim
39	106	Architectural implications of brick and mortar silicon manufacturing	claim
40	103	Ginger: control independence using tag rewriting	claim
41	94	Tailoring quantum architectures to implementation style: a quantum computer for mobile and persistent qubits	claim
42	92	Rotary router: an efficient architecture for CMP interconnection networks	claim
43	90	Transparent control independence (TCI)	claim

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