Sciweavers

104 search results - page 2 / 21
» A digit serial algorithm for the integer power operation
Sort
View
QSHINE
2005
IEEE
13 years 10 months ago
Link Scheduling with Power Control for Throughput Enhancement in Multihop Wireless Networks
Abstract— Throughput is an important performance consideration for multihop wireless networks. In this paper, we study the joint link scheduling and power control problem, focusi...
Jian Tang, Guoliang Xue, Christopher Chandler, Wei...
ISCAS
2002
IEEE
92views Hardware» more  ISCAS 2002»
13 years 10 months ago
Low cost floating-point unit design for audio applications
This paper presents a low-cost, single-cycle floating-point unit developed for digital audio processing applications. In the unit, the serial steps of floating-point operations ar...
Sung-Won Lee, In-Cheol Park
ICCD
2007
IEEE
746views Hardware» more  ICCD 2007»
14 years 2 months ago
Hardware design of a Binary Integer Decimal-based floating-point adder
Because of the growing importance of decimal floating-point (DFP) arithmetic, specifications for it are included in the IEEE Draft Standard for Floating-point Arithmetic (IEEE P75...
Charles Tsen, Sonia Gonzalez-Navarro, Michael J. S...
DATE
2009
IEEE
88views Hardware» more  DATE 2009»
14 years 20 hour ago
Multi-core for mobile phones
—High-end mobile phones support multiple radio standards and a rich suite of applications, which involves advanced radio, audio, video, and graphics processing. The overall digit...
C. H. van Berkel
CG
2002
Springer
13 years 5 months ago
Speeder Reader: An experiment in the future of reading
Speeder Reader is an interactive reading station built around two primary ideas: dynamic text (especially RSVP, that is, rapid serial visual presentation), and the interface metap...
Maribeth Back, Jonathan Cohen, Steve R. Harrison, ...