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ICCD
2006
IEEE
113views Hardware» more  ICCD 2006»
14 years 1 months ago
High-speed Factorization Architecture for Soft-decision Reed-Solomon Decoding
Reed-Solomon (RS) codes are among the most widely utilized error-correcting codes in modern communication and computer systems. Among the decoding algorithms of RS codes, the rece...
Xinmiao Zhang
CODES
2003
IEEE
13 years 10 months ago
Design space exploration of a hardware-software co-designed GF(2m) galois field processor for forward error correction and crypt
This paper describes a hardware-software co-design approach for flexible programmable Galois Field Processing for applications which require operations over GF(2m ), such as RS an...
Wei Ming Lim, Mohammed Benaissa
PDPTA
2000
13 years 6 months ago
Fast Communication Mechanisms in Coarse-grained Dynamically Reconfigurable Array Architectures
The paper focuses on coarse-grained dynamically reconfigurable array architectures promising performance and flexibility for different challenging application areas, e. g. future ...
Jürgen Becker, Manfred Glesner, Ahmad Alsolai...
VLSISP
2008
123views more  VLSISP 2008»
13 years 4 months ago
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. W...
ISCAS
2007
IEEE
99views Hardware» more  ISCAS 2007»
13 years 11 months ago
A Parallel Architecture for Hermitian Decoders: Satisfying Resource and Throughput Constraints
— Hermitian Codes offer desirable properties such as large code lengths, good error-correction at high code rates, etc. The main problem in making Hermitian codes practical is to...
Rachit Agarwal, Emanuel M. Popovici, Brendan O'Fly...