VLSISP 2008 - PDF Preprint Papers

VLSISP 2008

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VLSISP
2008

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An Embedded Real-Time Surveillance System: Implementation and Evaluation

13 years 4 months ago

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This paper presents the design of an embedded automated digital video surveillance system with real-time performance. Hardware accelerators for video segmentation, morphological op...

Fredrik Kristensen, Hugo Hedberg, Hongtu Jiang, Pe...

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Id	Views	Title	Status

1	239	An Embedded Real-Time Surveillance System: Implementation and Evaluation	claim
2	203	FPGA-based System for Real-Time Video Texture Analysis	claim
3	191	Accurate and Scalable Simulation of Network of Heterogeneous Sensor Devices	claim
4	173	Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity Microprocessors	claim
5	159	Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores	claim
6	147	Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder	claim
7	145	Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box	claim
8	140	Regular Expression Matching in Reconfigurable Hardware	claim
9	139	Fault Tolerance Analysis of Communication System Interleavers: the 802.11a Case Study	claim
10	134	Calibration of Abstract Performance Models for System-Level Design Space Exploration	claim
11	132	Serial and Parallel FPGA-based Variable Block Size Motion Estimation Processors	claim
12	132	Scenario Selection and Prediction for DVS-Aware Scheduling of Multimedia Applications	claim
13	130	Analysis and Hardware Architecture Design of Global Motion Estimation	claim
14	129	Architecture and Evaluation of an Asynchronous Array of Simple Processors	claim
15	123	Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder	claim
16	118	Analysis of Lifting and B-Spline DWT Implementations for Implantable Neuroprosthetics	claim
17	111	Design Methodology for Throughput Optimum Architectures of Hash Algorithms of the MD4-class	claim
18	108	Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays	claim
19	106	Architecture Considerations for Multi-Format Programmable Video Processors	claim
20	104	Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications	claim
21	103	Power Signature Watermarking of IP Cores for FPGAs	claim
22	102	VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC	claim
23	100	Memory-constrained Block Processing for DSP Software Optimization	claim
24	95	Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead	claim
25	95	A New Routing Metric for Satisfying Both Energy and Delay Constraints in Wireless Sensor Networks	claim
26	93	Performance and Energy Consumption Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path	claim
27	61	A Dynamic Voltage Scaling Algorithm for Dynamic Workloads	claim

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