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» A fast simulation approach for inductive effects of VLSI int...
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ICCD
2005
IEEE
221views Hardware» more  ICCD 2005»
14 years 1 months ago
Broadband Impedance Matching for Inductive Interconnect in VLSI Packages
Abstract— Noise induced by impedance discontinuities from VLSI packaging is one of the leading challenges facing system level designers in the next decade. The performance of IC ...
Brock J. LaMeres, Sunil P. Khatri
VLSID
2000
IEEE
102views VLSI» more  VLSID 2000»
13 years 9 months ago
Inductance Characterization of Small Interconnects Using Test-Signal Method
The test signal method can be used to measure and model inductance parameters (self and mutual) of a very small interconnect especially in highdensity IC’s by using a test signa...
Jeegar Tilak Shah, Madhav P. Desai, Sugata Sanyal
ISCAS
2006
IEEE
112views Hardware» more  ISCAS 2006»
13 years 10 months ago
Inductance extraction for general interconnect structures
As the operation frequency reaches gigahertz in very deep-submicron designs, the effect of on-chip inductance on circuit performance can no longer be neglected. Therefore, it is d...
Chun-Ying Lai, Shyh-Kang Jeng, Yao-Wen Chang, Chia...
DAC
2003
ACM
14 years 5 months ago
Efficient model order reduction including skin effect
Skin effect makes interconnect resistance and inductance frequency dependent. This paper addresses the problem of efficiently estimating the signal characteristics of any RLC netw...
Shizhong Mei, Chirayu S. Amin, Yehea I. Ismail
ISCAS
1999
IEEE
106views Hardware» more  ISCAS 1999»
13 years 9 months ago
Repeater insertion in RLC lines for minimum propagation delay
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
Yehea I. Ismail, Eby G. Friedman