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» A fill-unit approach to multiple instruction issue
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MICRO
1995
IEEE
97views Hardware» more  MICRO 1995»
14 years 2 months ago
Improving CISC instruction decoding performance using a fill unit
Current superscalar processors, both RISC and CISC, require substantial instruction fetch and decode bandwidth to keep multiple functional units utilized. While CISC instructions ...
Mark Smotherman, Manoj Franklin
MICRO
1994
IEEE
96views Hardware» more  MICRO 1994»
14 years 2 months ago
A fill-unit approach to multiple instruction issue
Multiple issue of instructions occurs in superscalar and VLIW machines. This paper investigates a third type of machine design, which combines the advantages of code compatibility...
Manoj Franklin, Mark Smotherman
MICRO
1991
IEEE
85views Hardware» more  MICRO 1991»
14 years 2 months ago
Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue Processors
This paper examines two alternative approaches to supporting code scheduling for multiple-instruction-issue processors. One is to provide a set of non-trapping instructions so tha...
Pohua P. Chang, William Y. Chen, Scott A. Mahlke, ...
IJAIT
2008
99views more  IJAIT 2008»
13 years 10 months ago
Optimal Basic Block Instruction Scheduling for Multiple-Issue Processors Using Constraint Programming
Instruction scheduling is one of the most important steps for improving the performance of object code produced by a compiler. A fundamental problem that arises in instruction sch...
Abid M. Malik, Jim McInnes, Peter van Beek
DATE
2008
IEEE
107views Hardware» more  DATE 2008»
14 years 5 months ago
Instruction Set Extension Exploration in Multiple-Issue Architecture
To satisfy high-performance computing demand in modern embedded devices, current embedded processor architectures provide designer with possibility either to define customized ins...
I-Wei Wu, Zhi-Yuan Chen, Jean Jyh-Jiun Shann, Chun...