Improving CISC instruction decoding performance using a fill unit

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Improving CISC instruction decoding performance using a fill unit
Current superscalar processors, both RISC and CISC, require substantial instruction fetch and decode bandwidth to keep multiple functional units utilized. While CISC instructions can sometimes provide reduced fetch bandwidth requirements, they are correspondingly more dicult to decode. A hardware assist, called a ll unit, can dynamically collect decoded microoperations into a decoded instruction cache. Future code fetches to those locations can be satis ed out of this cache and thus bypass the decoding logic. This approach is investigated using the Intel x86 architecture, and a speedup of approximately a factor of two over a P6-like decoding structure is seen for the three SPEC benchmarks investigated. This design is accompanied by a microengine-register allocation and renaming scheme that prevents the increased supply of microoperations from placing excessive demands on the normal register renaming hardware.
Mark Smotherman, Manoj Franklin
Added 26 Aug 2010
Updated 26 Aug 2010
Type Conference
Year 1995
Authors Mark Smotherman, Manoj Franklin
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