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TCAD
2008
103views more  TCAD 2008»
13 years 5 months ago
Topology-Based Performance Analysis and Optimization of Latency-Insensitive Systems
Latency-insensitive protocols allow system-on-chip (SoC) engineers to decouple the design of the computing cores from the design of the intercore communication channels while follo...
Rebecca L. Collins, Luca P. Carloni
CDES
2006
184views Hardware» more  CDES 2006»
13 years 7 months ago
Compilation for Future Nanocomputer Architectures
Compilation has a long history of translating a programmer's human-readable code into machine instructions designed to make good use of a specific target computer. In this pa...
Thomas P. Way
CONCURRENCY
2000
83views more  CONCURRENCY 2000»
13 years 5 months ago
Javia: A Java interface to the virtual interface architecture
The Virtual Interface (VI) architecture has become the industry standard for user-level network interfaces. This paper presents the implementation and evaluation of Javia, a Java ...
Chi-Chao Chang, Thorsten von Eicken
ISCA
1997
IEEE
137views Hardware» more  ISCA 1997»
13 years 10 months ago
A Language for Describing Predictors and Its Application to Automatic Synthesis
As processor architectures have increased their reliance on speculative execution to improve performance, the importance of accurate prediction of what to execute speculatively ha...
Joel S. Emer, Nicholas C. Gloy
INFOCOM
2010
IEEE
13 years 4 months ago
Linear Programming Models For Multi-Channel P2P Streaming Systems
Abstract—Most of the commercial P2P video streaming deployments support hundreds of channels and are referred to as multichannel systems. Measurement studies show that bandwidth r...
Miao Wang, Lisong Xu, Byrav Ramamurthy