3 search results - page 1 / 1 » A fully associative software-managed cache design |
ISCA
2000
IEEE
13 years 9 months ago
2000
IEEE
As DRAM access latencies approach a thousand instructionexecution times and on-chip caches grow to multiple megabytes, it is not clear that conventional cache structures continue ...
HPCA
2009
IEEE
14 years 6 months ago
2009
IEEE
Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...
MDM
2005
Springer
13 years 11 months ago
2005
Springer
Data access prediction has been proposed as a mechanism to overcome latency lag, and more recently as a means of conserving energy in mobile systems. We present a fully adaptive p...