326 search results - page 1 / 66 » A hierarchical modeling framework for on-chip communication ... |
HPCA
2009
IEEE
14 years 5 months ago
2009
IEEE
Driven by continuing scaling of Moore's law, chip multiprocessors and systems-on-a-chip are expected to grow the core count from dozens today to hundreds in the near future. ...
ICCD
2002
IEEE
14 years 1 months ago
2002
IEEE
Interconnect architecture plays an important role in determining the throughput of meshed communication structures. We assume a mesh structure with uniform communication demand fo...
AINA
2009
IEEE
13 years 11 months ago
2009
IEEE
This paper presents a novel analytical model to compute communication latency of broadcast as the most fundamental collective communication operation. The novelty of the model lie...
DAC
1999
ACM
14 years 5 months ago
1999
ACM
Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] ...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
Interconnect networks play a critical role in shared memory multiprocessor systems-on-chip (MPSoC) designs. MPSoC performance and power consumption are greatly affected by the pac...